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PRELIMINARY DATA SHEET
256MB Unbuffered SDRAM Micro DIMM
HB52RF328GB-B (32M words x 64 bits, 1 bank) HB52RD328GB-B (32M words x 64 bits, 1 bank)
Description
The HB52RF328GB and HB52RD328GB are a 32M x 64 x 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 8 pieces of 256M bits SDRAM (HM522805BTB/BLTB) sealed in TCP package and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
Features
* 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 38.00mm (Length) x 30.00mm (Height) x 3.80mm (Thickness) Lead pitch: 0.50mm * 3.3V power supply * Clock frequency: 133MHz/100MHz (max.) * LVTTL interface * Data bus width: x 64 Non parity * Single pulsed /RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8 * 2 variations of burst sequence Sequential Interleave * Programmable /CE latency (CL): 2, 3 * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current : HB52RF328GB-xxBL : HB52RD328GB-xxBL
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Document No. E0202H10 (Ver. 1.0) Date Published August 2001 (K) Printed in Japan URL: http://www.elpida.com
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This product became EOL in September, 2002.
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Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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Elpida Memory, Inc. 2001
HB52RF328GB-B, HB52RD328GB-B
Ordering Information
Part number HB52RF328GB-75B*1 HB52RF328GB-75BL*1 HB52RD328GB-A6B HB52RD328GB-A6BL HB52RD328GB-B6B*2 HB52RD328GB-B6BL*2 Clock frequency MHz (max.) 133 133 100 100 100 100 /CE latency 3 3 2, 3 2, 3 3 3 Package Micro DIMM (144-pin) Contact pad Gold
Notes: 1. 100MHz operation at /CE latency = 2. 2. 66MHz operation at /CE latency = 2.
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Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS VCC A0 A1 A2 VSS
Pin Configurations
Front Side
1pin 2pin
143pin 144pin
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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Pin name Pin No. 73 75 77 79 81 83 85 87 89 91 93 DQMB0 DQMB1 95 97 99 101 103 105 107
Back Side
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Back side Pin No. Pin name Pin name Pin No. NC 2 VSS 74 VSS 4 DQ32 76 NC NC 6 8 DQ33 DQ34 78 80 NC NC VCC 10 DQ35 82 DQ16 12 VCC 84 DQ17 DQ18 DQ19 VSS 14 16 18 DQ36 DQ37 DQ38 86 88 90 20 DQ39 92 DQ20 22 VSS 94 DQ21 DQ22 24 26 DQMB4 DQMB5 96 98 DQ23 28 VCC A3 A4 A5 VSS 100 VCC A6 A8 VSS 30 32 34 36 102 104 106 A7 108
Pin name
CK1 VSS
VCC DQ48
DQ49 DQ50 DQ51 VSS
DQ52
DQ53 DQ54 DQ55
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VCC BA0 VSS
2
HB52RF328GB-B, HB52RD328GB-B
Front side Pin No. 37 39 41 43 45 47 49 51 53 Pin name DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS Pin No. 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 Pin name A9 A10 (AP) VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC
Back side Pin No. 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin name DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VCC /CE NC A12 NC Pin No. 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Pin name BA1 A11 VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
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55 57 NC 59 NC 61 63 CK0 VCC /RE /W 65 67 69 71 /S0 NC
Pin Description
Pin name A0 to A12
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139 141 143
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Function Address input -- Row address A0 to A12 -- Column address A0 to A9 Bank select address Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground
BA0, BA1 DQ0 to DQ63 /S0 /RE /CE /W DQMB0 to DQMB7 CK0, CK1 CKE0 SDA SCL VCC VSS NC
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No connection
Preliminary Data Sheet E0202H10 (Ver. 1.0)
3
HB52RF328GB-B, HB52RD328GB-B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 80 08 04 0D 0A 01 40 00 01 75 A0 54 60 00 82 08 00
Comments 128 256byte SDRAM 13 10 1 64 0 (+) LVTTL CL = 3
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 (-B6) 15ns 24 (-B6) 8ns 25
SDRAM cycle time (highest /CE latency) (-75) 7.5ns (-A6, -B6) 10ns
SDRAM access from Clock (highest /CE latency) 0 (-75) 5.4ns
Module configuration type Refresh rate/type SDRAM width
Error checking SDRAM width
SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CE latency SDRAM device attributes: /S latency SDRAM device attributes: /W latency SDRAM module attributes
SDRAM device attributes: General SDRAM cycle time (2nd highest /CE latency) (-75/A6) 10ns
SDRAM access from Clock (2nd highest /CE latency) (-75/A6) 6ns SDRAM cycle time (3rd highest /CE latency) Undefined
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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(-A6, -B6) 6ns
0 0 1 0 0
Non parity Normal (7.8125s) Self refresh x8 --
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0 0 0 0 0 0 0 0 0 0 0 0 1 01 1 CLK 0 0 0 1 1 1 1 0F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 04 06 01 01 4 2, 3 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 1 1 1 0 0E 1 0 1 0 0 0 0 0 A0 CL = 2 1 1 1 1 0 0 0 0 F0 0 1 1 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 00
1, 2, 4, 8
Unbuffer
VCC 10%
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4
HB52RF328GB-B, HB52RD328GB-B
Byte No. 26 27 28 Function described SDRAM access from Clock (3rd highest /CE latency) Undefined Minimum row precharge time Row active to row active min (-75) (-A6, -B6) 29 30 /RE to /CE delay min Minimum /RE pulse width (-75) (-A6, -B6) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 00 14 0F 14 14 2D 32 40 15 20 08 10 15 20 08 10 00 20ns 15ns 20ns 20ns 45ns 50ns 256M byte 1.5ns 2.0ns 0.8ns 1.0ns 1.5ns 2.0ns 0.8ns 1.0ns Future use Comments
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31 32 (-A6, -B6) 33 (-A6, -B6) 34 (-A6, -B6) 35 (-A6, -B6) 36 to 61 62 63 (-A6B/BL) (-B6B/BL) 64 65 to 71 72 73 74 75 76 77 78 (-A6, -B6) 79 80 81 82 83 84
Density of each bank on module Address and command signal input setup time (-75) Address and command signal input hold time (-75) Data signal input setup time (-75) Data signal input hold time (-75)
Superset information
SPD data revision code
Checksum for bytes 0 to 62 (-75B/BL)
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location
Manufacturer's part number Manufacturer's part number
Manufacturer's part number Manufacturer's part number Manufacturer's part number
Manufacturer's part number (-75)
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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0 0 1 0 1 0 0 1 0 12 0 0 1 0 0 1 0 52 82 1 0 1 1 1 0 0 1 B9 185 0 0 1 0 1 0 0 1 29 41 0 0 0 0 0 1 1 1 07 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 00 xx 0 1 0 0 1 0 0 0 48 H 0 1 0 0 0 0 1 0 42 B 5 2 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 35 32 0 1 0 1 0 0 1 0 52 R F 0 1 0 0 0 1 1 0 46 0 1 0 0 0 1 0 0 44 D 3 2 8 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 33 32 38 47 42 2D G B
Rev. 1.2B
HITACHI
*2 (ASCII-8bit code)
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5
HB52RF328GB-B, HB52RD328GB-B
Byte No. 85 Function described Manufacturer's part number (-75) (-A6) (-B6) 86 Manufacturer's part number (-75) (-A6, -B6) 87 88 Manufacturer's part number Manufacturer's part number (-xxB) (-xxBL) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 x x *3 -- 0 1 1 -- 1 0 0 -- 1 0 0 -- 0 0 0 -- 0 0 0 -- 1 1 1 -- 0 1 0 -- 0 1 1 -- 64 87 85 *4 100MHz CL = 2, 3 CL = 3 0 1 1 0 0 1 0 1 0 0 0 0 x x 1 0 0 1 1 0 1 0 1 1 1 1 x x 1 0 0 1 1 0 0 0 0 0 1 0 x x 0 0 0 0 0 0 0 1 0 0 0 0 x x 1 0 0 1 1 0 0 1 0 0 0 0 x x 1 0 1 0 1 1 0 0 0 0 0 0 x x 1 1 0 1 0 0 0 0 0 0 0 0 x x 37 41 42 35 36 42 20 4C 20 20 30 20 xx xx Comments 7 A B 5 6 B (Space) L (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
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89 90 91 92 93 94 95 to 98 99 to 125 126 127 (-B6)
Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date
Assembly serial number Manufacturer specific data
Intel specification frequency
Intel specification /CE# latency support (-75/A6)
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High". These SPD are based on Rev.1.2B specification. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0").
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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HB52RF328GB-B, HB52RD328GB-B
Block Diagram
/S0 /W DQMB0 /CS DQMB1 /CS
D0
8 N0, N1 DQ0 to DQ7 DQ8 to DQ15 8 N8, N9
D1
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/RE /CE A0 to A12 BA0 BA1 CKE0 CK0 VCC VSS CK1
DQMB2
/CS
DQMB3
/CS
D2
8 N2, N3 DQ24 to DQ31 8 N10, N11
D3
DQ16 to DQ23
DQMB4
/CS
DQMB5
/CS
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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DQ32 to DQ39 DQMB6 DQ48 to DQ55
C100 to C118
D4
8 N12, N13 DQ40 to DQ47
D5
8 N4, N5
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/CS DQMB7 /CS
D6
D7
8 N6, N7
8 N14, N15
DQ55 to DQ64
/RAS (D0 to D7) /CAS (D0 to D7)
Serial PD
SCL
SCL A0 A1 A2
SDA
SDA
A0 to A12 (D0 to D7) BA0 (D0 to D7) BA1 (D0 to D7)
U0
CKE (D0 to D7) CLK (D0 to D7)
VCC (D0 to D7) VSS (D0 to D7)
VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
10 10pF
* D0 to D7: HM5225805 U0: 2k bits EEPROM C100 to C118: 0.1F N0 to N15: Network resistors (10)
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7
HB52RF328GB-B, HB52RD328GB-B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC IOUT PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max.)) -0.5 to +4.6 50 8.0 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1
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Parameter Supply voltage Input high voltage Input low voltage Ambient illuminance
Note: 1. Respect to VSS.
DC Operating Conditions (TA = 0 to +65C)
Symbol VCC VSS VIH VIL -- min. 3.0 0 2.0 -0.3 -- max. 3.6 0 VCC + 0.3 0.8 100 Unit V V V V lx Note 1, 2 3 1, 4 1, 5
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Notes: 1. 2. 3. 4. 5.
All voltage referred to VSS. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VCC + 2.0V for pulse width 3ns at VCC. VIL (min.) = VSS - 2.0V for pulse width 3ns at VSS.
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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HB52RF328GB-B, HB52RD328GB-B
DC Characteristics 1 (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Parameter Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CL = 2) (CL = 3) Symbol ICC1 Grade -75 -A6 -B6 -75 -A6 -B6 Max. 880 760 600 880 760 760 24 16 160 32 240 -75 -A6 -B6 -75 -A6 -B6 800 800 600 1080 800 800 1760 24 16 Unit mA Test conditions Burst length = 1 tRC = min. Notes 1, 2, 3
ICC1 ICC2P ICC2PS ICC2N ICC3P ICC3N ICC4
mA mA mA mA mA mA mA CKE0 = VIL, tCK = 12ns CKE0 = VIL, tCK = CKE0, /S = VIH, tCK = 12ns CKE0, /S = VIH, tCK = 12ns CKE0, /S = VIH, tCK = 12ns tCK = min., BL = 4 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5
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Refresh current Self refresh current Self refresh current (L-version) Parameter Input leakage current Output leakage current Output high voltage Output low voltage
ICC4 ICC5 ICC6
mA mA mA mA tRC = min. VIH VCC - 0.2V VIL 0.2V 3 8
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current. DC Characteristics 2 (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Symbol Grade min. -10 Max.
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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ILI ILO VOL
ICC6
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Unit Test conditions 10 A 0 Vin VCC -10 2.4 -- 10 -- A V 0 Vout VCC DQ = disable VOH IOH = -4 mA IOL = 4 mA 0.4 V
Notes
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9
HB52RF328GB-B, HB52RD328GB-B
Pin Capacitance (TA = 25C, VCC = 3.3V 0.3V)
Parameter Input capacitance Input capacitance Input capacitance Input capacitance Input/Output capacitance Symbol CIN CIN CIN CIN CI/O Pins Address /RE, /CE, /W, CK0/CK1, CKE0 /S0 DQMB DQ max. 80 80 80 20 20 Unit pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Notes: 1. 2. 3. 4.
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
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Parameter (CL = 3) CK high pulse width CK low pulse width Access time from CK (CL = 2) (CL = 3) Data-out hold time Input setup time Refresh period
AC Characteristics (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
-75 Symbol tCK tCK PC100 Symbol Tclk Tclk Tch Tcl Tac Tac min. 10 7.5 2.5 2.5 -- -- max. -- -- -- -- 6 5.4 -- -A6 min. 10 10 3 3 -- -- 3 max. -- -- -- -- 6 6 -B6 min. 15 10 3 3 -- -- 3 max. -- -- -- -- 8 6 Unit ns ns ns ns ns ns 1 1 1, 2 Notes 1
System clock cycle time (CL = 2)
CK to Data-out low impedance
CK to Data-out high impedance tHZ
CKE setup time for power down tCESP exit tAH, tCH, Input hold time tDH, tCEH Ref/Active to Ref/Active tRC command period Active to Precharge command tRAS period Active command to column tRCD command (same bank) Precharge to active command tRP period Write recovery or data-in to tDPL precharge lead time Active (a) to Active (b) tRRD command period Transition time (rise and fall) tT tREF
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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tCKH tCKL tAC tAC tOH tLZ
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Toh 2.7 -- -- ns 2 -- 2 -- 6 2 -- 6 ns -- 5.4 -- -- -- ns tAS, tCS, Tsi tDS, tCES 1.5 2 -- 2 -- ns Tpde Thi 1.5 -- 2 -- 2 -- ns 1 0.8 -- 1 -- 1 -- ns 1 Trc 67.5 -- 70 -- 70 -- ns 1 Tras 45 120000 -- 50 120000 50 -- 120000 ns -- 1 Trcd 20 20 20 ns 1 Trp 20 -- 20 -- 20 -- ns 1 Tdpl Trrd 15 -- 20 20 -- 20 20 -- ns ns 1 15 -- -- -- 5 1 1 -- 5 64 1 -- 5 64 1 -- ns 64 ms
1, 2
1, 2, 3 1, 4
1, 5
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10
HB52RF328GB-B, HB52RD328GB-B
Notes: 1. 2. 3. 4. 5. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V. Access time is measured at 1.5V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state. tCES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5V * Input waveform and output load: See following figures
2.4V 0.4V 2.0V 0.8V
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input
I/O CL tT
tT
Input waveform and output load
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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HB52RF328GB-B, HB52RD328GB-B
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CL = 2) (CL = 3) Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lAPW lSEC lHZP lHZP lAPR lEP Troh Troh Tsrx Tdal Tdpl PC100 Symbol -75 133 7.5 3 9 6 3 2 2 1 5 9 2 3 1 -1 -A6, -B6 100 10 2 7 5 2 2 2 1 4 7 2 3 1 -1 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
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(CL = 3) DQMB to data in DQMB to data out CKE to CK disable /S to command disable
Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CL = 2)
Column command to column command Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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lEP -2 -2 lCCD Tccd 1 1 lWCD Tdwd 0 0 lDID Tdqm 0 0 lDOD lCLE Tdqz Tcke 2 2 1 1 lRSA Tmrd 1 1 lCDD lPEC 0 0 1 1
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12
HB52RF328GB-B, HB52RD328GB-B
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /S0 (input pin): When /S is Low, the command input cycle becomes valid. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RE, /CE and /W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0, BA1(BA) is precharged. BA0, BA1 (input pin): BA0, BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is Low and BA1 is High, bank1 is selected. If BA0 is High and BA1 is Low, bank2 is selected. If BA0 is High and BA1 is High, bank3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3V is applied.
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VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.(E0082H)
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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HB52RF328GB-B, HB52RD328GB-B
Physical Outline
42.0 max. (38.0) 1.0 min. 1.0 min. 3.80 max.
Unit: mm
4-R1.0 0.1
1.0 min.
Detail A
Detail B
4.0 0.1
5.0 0.1
0.37 0.03
1.0 0.08
0.25 max.
ECA-TS2-0028-01
Preliminary Data Sheet E0202H10 (Ver. 1.0)
14
2.00 min.
2
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30.0
15.0
1
A 17.625 35.50 37.0 0.08 35.50 17.875
B 0.80 0.08 0.875
R1.0 0.1
Component area (back)
2.5 min.
0.625
1.0 min.
3.5 min.
3.5 min.
Component area (front)
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0.50
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HB52RF328GB-B, HB52RD328GB-B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
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1 2 3
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0202H10 (Ver. 1.0)
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HB52RF328GB-B, HB52RD328GB-B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
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Preliminary Data Sheet E0202H10 (Ver. 1.0)
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